Method for making a high voltage semiconductor device



March 14, 1967 J. c. HAENICHEN METHOD FOR MAKING A HIGH VOLTAGESEMICONDUCTOR DEVICE 8 Sheets-Sheet 1 Original Filed Nov. 4;, 1963 Fig.2

INVENTOR. John C. Haen/chen M, W, W

March 14, 1967 J. c. HAENICHEN 3,309,24g

METHOD FOR MAKING A HIGH VOLTAGE SEMICONDUCTOR DEVICE Original FiledNov. 4, 1 963 8 Sheets-Sheet 2 Fig.

m E S 2 z o O 0 Lu 2 Demh & v 08pm INVFNTOR. fHiCK S102 FILM THEN SlOgFILM John CHaenichen ELECTRON CONCENTRATION BY vs DEPTH IN SILICON z j aa 5M 6 ATTYS.

arch 14, 1967 J- c. HAENICHEN 3,309,24

METHOD FOR MAKING A HIGH VOLTAGE SEMICONDUCTOR DEVICE Original FiledNov. 4, 1963 8 Sheets-Sheet :5

7/ //7/7/ /F/V c 7 Q 0 w 42 (Pg) I I NVENTOR 48 John C. Haenichen W,WMW

ATTYS.

March 14, 1967 J. CHAENICHEN 3,309,246

METHOD FOR MAKING A HIGH VOLTAGE SEMICONDUCTOR DEVICE Original Filed.NOV. 4, 1963 v- '8 Sheets-Sheet IN\-ENTOR. John C. Haenichen ATTY'S,

March 14, 1967 J. c. HAENICHEN METHOD FOR MAKING A HIGH VOLTAGESEMICONDUCTOR DEVICE Original Filed NOV. 4, 1963 8 Sheets-Sheet 5 Fig?JNVENTOR. John C. Haenichen a? W,WW

A'rrY's.

14, 1967 J. c. HAENICHEN 3,309,246

METHOD FOR MAKING A HIGH VOLTAGE SEMICONDUCTOR DEVICE OriginalFiled-Nov. 4., 1963 's Sheats-Sheet e INVENTOIL John Cv HaenichelsATTY'S.

- M r h 3967 J. c. HAENICHEN 3,309,246

METHOD FOR MAKING A HIGH VOLTAGE SEMICONDUCTOR DEVICE Original FiledNov. 4, 1963 8 Sheets-Sheet 7 92 B 93 92 I20 Qw W I n a? I B6 WW2 I 99I07 97 99 98 M76 INVENTOR.

m xx @091 m. WYZI W JohnCHenihn c I J ATTY'S.

March 14, 1967 J. c. HAENICHEN 3,309,246

METHOD FOR MAKING A HIGH VOLTAGE SEMICONDUCTOR DEVICE Original FiledNov. 4, 1963 a Sheets-Sheet a 8 lol 05 loam gm C /105 IO4JWIOS\ Q5122 yW' 7 'VY/Z J m i D lol I NVENTOR John C. Haenichen BY W MM MVJL/ ATTY'S,

3,309,246 METHQD FOR MAKHN G A HEGH VOLTAGE SEMTCONDUCTOR DEVICE John C.Haenichen, Scottsdale, Ariz., assignor to Motorola, Inc., Franklin Park,IlL, a corporation of Illinois Original application Nov. 4, 1963, Ser.No. 321,070, now Patent No. 3,226,614, dated Jan. 25, 1966. Divided andthis application Oct. 24, 1965, Ser. No. 504,813 Claims. (Cl. 148-187)This application is a division of copending application Ser. No.321,070, filed Nov. 4, 1963, now Patent No. 3,226,614 which is acontinuation-in-part of a copending application Ser. No. 265,649, filedMar. 18, 1963, now Patent No. 3,226,613.

This invention relates to semiconductor devices and particularly topassivated transistors and other semiconductor devices having improvedhigh voltage operating characteristics, and the method of making thesame.

It is generally true that compared to transistors which are operableonly at low voltages but are otherwise equivalent, high voltagetransistors are more dependable devices which are much less limited inthe manner in which they may be used.

High voltage transistors are characterized by their higher avalanchevoltage characteristic BV (the voltage acrossthe collector-to-basejunction at which avalanche breakdown occurs) which enables them tooperate over a wider voltage range from their minimum operable collectorvoltage up to their higher value of BV Having a higher BV high voltagetransistors are more reliable since when used under the same biasingconditions, they have a greater margin of safety against destructivesurges of voltage.

Transistors having a high BV demonstrate several desirablecharacteristics, they may be operated so as to have a higher poweroutput and a higher power gain as compared to lower voltage units. Highvoltage transistors may often be operated at power line or other sourcevoltages so that voltage reducing components or equipment areunnecessary.

The value of BV is usually the voltage at which avalanche breakdown ofthe collector-base junction occurs at the surface of the semiconductorcrystalline element rather than beneath in the bulk, since surfacebreakdown tends to occur at the lower voltage. In both the bulk andsurface cases, the voltage at which avalanche breakdown occurs has afunctional dependence on the resistivity of the semiconductor materialand may be increased by raising the resistivity of either the base orcollector or both. Additionally, the surface avalanche voltage is muchmore environment sensitive and dependent on the previous history of thecrystalline element with regard to how the semiconductor material wasgrown and how processed than is the bulk. Therefore, for stable andreproducible operation near avalanche voltage it is desirable to havethe surface breakdown voltage higher than that of the bulk material.

Surface effects of various types leading to reduced values of BV arecommon to both PNP and NPN transistors. It should be noted, too, thatprocessing requirements may lead to reduced values of BV for otherreasons. Wherever an oxide-silicon interface exists or forms while thesilicon is heated to temperatures high enough for significant solidstate diffusion to occur, the doping impurity of the silicon will beredistributed in both the silicon and the oxide according to thesegregation coefficient of the impurity at the interface between theoxide and the silicon, the diffusion coefficient for the impurity withrespect to the silicon and the oxide, the time heated, the temperature,and when applicable the rate and time of oxidation. For example, in themanu- States Patent 0 facture of certain types of diffused-base NPNsilicon transistors the silicon element is exposed to high temperatureoxidizing environments for prolonged periods of time to form silicondioxide or silicon dioxide bearing glass across the N type collectorregion. If the -N region is phosphorus doped for example, the oxidationsteps usually result in transistors with a degraded BV due to changes inthe doping concentration of the surface silicon. The phosphorus dopantin the silicon is only slightly soluble in. silicon dioxide andtherefore as the surface of the N type silicon is oxidized, thephosphorus from the oxidized silicon accumulates in front of the silicondioxide-silicon interface thus forming an N+ layer there. The N+ layerbecomes thicker and is pushed ahead of the interface as the siliconcontinues to be oxidized; this phenomenon is known as the snowploweffect and -N+ layer is known as the snowplow layer. When the P typebase region is subsequently diffused into the phosphorus doped collectorregion, the bulk portion of the junction is in N type silicon while thesurface portion of the junction is in N+ silicon. The result iscollectonto-base avalanche breakdown BV at voltages well below whatwould be the case for essentially the same device design without the N+layer at the collector surface. Had the original N type silicon beencompensated material containing certain P type impurities such as boron,the BV after heating would have been even lower. The segregation anddiffusion coefficients for boron are such that the boron moves readilyinto the oxide from the silicon near the oxide-silicon interfaceresulting in yet a larger concentration of uncompensated phosphorus inthe silicon near the interface.

The series resistance of a transistor is increased in raising BV by theuse of high resistivity collector material, frequently to the detrimentof a number of other device parameters, so that designers have had tomake a compromise with respect to BV in order to keep the seriesresistance at a satisfactorily low value. However, it is possible, in atransistor to increase the surface breakdown voltage by changing thecharacter of the surface where breakdown occurs so that for a givenseries resistance a higher BV is possible and it is toward this end thatthe present invention is directed.

Similarly, the same principles apply to increasing the avalanchebreakdown voltage of diodes and a variety of semiconductor deviceswithout degrading any of the related parameters of these devices.

Accordingly, the principal object of this invention is to increase theoperating voltage of transistors and other semiconductor devices withoutotherwise degrading them, and to do so, this invention features the useof a thin region or channel of a con-trolled size and geometry at thesurface of the semiconductor device which is of a higher resistivitythan the bulk semiconductor material so that avalanche breakdown for thedevice tends to occur in the bulk and therefore at a higher voltage.

In the accompanying drawings:

FIG. 1 is an isometric view of a transistor which has been fabricatedaccording to this invention;

FIG. 2 is a greatly enlarged isometric view of the active element of thetransistor of FIG. 1;

FIG. 3 is a cross sectional view of FIG. 2 taken at line 3-3;

FIG. 4 is an enlarged view of a portion of FIG. 3 to show the functionof the depletion region at the basecollector junction under reversebias;

FIG. 5 is a greatly enlarged view of a transistor which has beenfabricated so that it has an induced channel which has been adjusted bythinning the inducing silicon dioxide film;

FIG. 6 shows typical electron concentration distribu- :tions at thesurfaces of silicon beneath thick and thin silicon dioxide films whichhave been formed by oxidizing the silicon surface in an atmosphere ofsteam;

FIGS. 7, 8 and 9 each shows the steps in the preparation of a differentkind of transistor element having a thin surface region formed byepitaxial growth;

FIG. shows the steps in preparing an active element of a transistor witha thin surface region formed by diffusion during and subsequent toepitaxial growth;

FIGS. 11 and 12 show the steps in preparing two different kinds ofactive transistor elements, the thin surface regions of which areprepared using solid state diffusion techniques; and

FIGS. 13 and 14 show the steps in preparing different active transistorelements having induced channels which have been formed or adjusted bycoating with suitable silicon dioxide and/ or glass films. I p

A brief initial description of an embodiment of the invention is asfollows. Transistors, especially passivated transistors, are fabricatedso that the base region of the device is extended in a thin surfaceregion having a resistivity which is substantially higher than the bulkmaterial of the base. With this construction, avalanche breakdown occurspreferentially in the bulk material rather than at the much less stablesurface.

The thin extension of the base may be formed by epitaxial and diffusiontechniques or by induction. The thin region, called a channel,terminates in a low resistivity region of the opposite conductivitytype. This region geometrically describes the channel and preventsdevice degradation due to the accidental formation of induced channels.

Transistors so fabricated feature improved high voltage characteristics,stability, uniformity and reproducibility. Also, as applied to diodes,extension of one conductivity type region of a junction with a thinregion or channel or higher resistivity will provide similar advantages.

FIG. 1 is an isometric view of a high voltage passivated transistor 1,the active element 2 of which has been prepared in accordance with thisinvention. To show the construction of a typical finished embodiment ofthis invention, the device is shown greatly enlarged and the can 3 hasbeen cut away. The active element has been fused to the header body 4and connections from the emitter and base header leads 5 and 6 to theactive element 2 have been made by thermocompression bonding. The headercollector lead 7, in order to provide connection to the collector regionof the active element, has been bent over and welded to the body of theheader.

The isometric view shown in FIG. 2 is the active crystal element 2 ofthe transistor of FIG. 1. FIG. 3 is a cross sectional view of thetransistor taken at line 33. The basic device may be either of the PNPor NPN type. For explanation purposes, a PNP silicon transistor will beconsidered in detail and except for the modifications due to thedifferences in conductivity type material and the carriers involved, thetreatment may be considered as applicable to the NPN device.

Merely for illustrative purposes and to simplify the understanding ofthe structure shown in FIG. 3 of the drawings, conductivity types for aPNP transistor are indicated. In other figures of the drawings theindications are also illustrative unless the specification statesotherwise.

The active element 2 has been formed on a chip 12 or substrate of Pconductivity type silicon. The substrate may be more heavily doped withacceptor impurity to form a P-{ region 13 near the bottom of the deviceso as to have the series resistance of the transistor at a low value.The emitter 14 and base regions 15 of the transistor may be formed bysolid state diffusion or epitaxially, and the remainder of the P typechip 12 is the collector of the device. The device may be passivated asan option by coating with a film of silicon dioxide 16 or other suitablematerial. The usual contact regions 17, 18 and 19 are of metal.

4 In accordance with the invention, the transistor is equipped with achannel 20 of high resistivity silicon at the surface which slightlyextends the base 15 of the tran; sister. The channel is terminated by aperimeter 21 of P+ silicon a short distance from the base. In theremainder of this specification, such a terminal region or itsequivalent will be referred to as the perimeter of the device. I Theterm channel-interrupting region has been used in prior-filed relatedapplications to mean the same perimeter herein, and for uniformity amongall such 'ap= plications, it will also be used herein. Theseapplications are Serial No. 218,904, filed August 23, 1962, Patent No.3,226,611, Ser. No. 265,736 filed Mar. 18, 1963, Patent No. 3,226,612,Set. No; 265,649, filed Mar. 18; 1963 Patent No. 3,226,613, Ser. No.321,070, filedNov. 4, 1963, Patent No. 3,226,614, and Ser. No. 465,012,filed June 18,1965.

The channel region 20 is formed so as to have a substantially higherresistivity than the rest of the base region. The channel is alsodimensionally adequate so that the depletion region may form into itwithout restriction to the extent possible according to the resistivityof this niaterial. Satisfaction of these two channel requirements,higher resistivity material than in the base region and a channel longenough for adequate depletion region spreading will satisfactorily raisethe breakdown for the ideal transistor but this is not necessarily truein the practical case. As will be shown for the practical case, theperimeter 21 of P+ material is necessary.

As shown in FIGS. 2 and 3, the N- channel is interrupted a shortdistance from the base by a region 21 of P+ silicon. The balance of theoriginal channel region is the region 22. Obviously, if the channelextends across the face of the chip, the capacitance of the device wouldbe very high and so this P+ region 21 defines geometri cally theperiphery 23 of the collector-base junction of the transistor, but thisvery useful function is not of first importance since well-known methodspermit such a re= gion to be defined in other ways. However,interrupting the channel with this perimeter 21 of P+ material to shapeit to a given geometry is desirable over known alternative methods sincethe perimeter is also useful in minimizing the effect of inducedchannels that might possibly form. Operating conditions, storageconditions and especially changes in the ambient atmosphere in which atransistor is encapsulated may, for a variety of reasons includingexposure to an ionizing or radioactive environment, alfect the surfaceof a transistor in such a manner as to cause the formation of conductiveinduced channels or inversion layers leading from the base to regions ofhigh recombination or leakage. The presence of such induced channels,when of the same conductivity type as the base and where accidental, mayseriously degrade the device and possibly render it unserviceable.Fortunately, induced channels having a very high net carrierconcentration are exceptional and thus induced channels of a givenconductivity type terminate in low resistivity regions of the oppositeconductivity type. Thus, the perimeter 21 of P+ material in the PNPtransistor performs double service in that it defines the geometry ofthe true or primary channel and improves the reliability of thetransistor by terminating or interrupting induced channels and solargely eliminating their adverse effect. For the NPN transistor, theperimeter is, of course, an N+ region.

A portion of a passivated transistor is shown greatly enlarged in FIG.4. Consideration of this figure is useful in discussing the structureand operation of the high voltage transistor of this invention. When thenormal reverse bias is applied to the base-collector junction 23 and 24of a PNP silicon transistor, for example, a depletion region 25 forms,the thickness of which depends on the voltage applied and on theresistivity and conductivity type of the silicon. For a givenresistivity of a particular conductivity type of silicon, the depletionregion spreads with voltage until a maximum thickness is achieved afterwhich a further voltage increase does not spread the region further butinstead causes avalanche breakdown to occur. In a relatively heavilydoped base region 15, the depletion region shown by the thickness A, israther slight corresponding to a small voltage, and the balance of thespreading B is into the lightly doped P- collector region so that thetotal thickness within the bulk is A+B which is a maximum just beforeavalanche breakdown.

At the surface of the transistor, part C of the depletion region spreadseasily into the lightly doped channel 20 and part D only slightly intothe P+ perimeter 21 so that the total thickness is C+D. If C-l-D is ableto spread to a maximum value corresponding to a voltage greater thanthat for a maximum value of A+B aywhere within the bulk, then avalanchebreakdown occurs preferentially within the device rather than at thenormally less stable surface as is generally the case. In most cases theresult is a transistor whose breakdown voltage is quite stableregardless of environment and one whose avalanche voltage rating BV issignificantly higher than it would be without the channel.

Alternatively, in the PNP device, a similar improved breakdown effectmay be obtained by forming a thin very high resistivity P region at thesurface adjacent the N type base. However, the P+ region 21 is stillrequired for maximum reliability since it acts to preclude formation ofa conductive path from the base represented by the occasional N typeinduced channel which might form at the surface of the thin P region andwhich would tend to degrade the transistor.

Induced channels may be controlled by carefully controlling theenvironment in which the active element operates, e.g., the atmospherein which it is encapsulated. Additionally, where induced channels arecaused to form by thin films, the concentration and distribution ofcarriers may be adjusted by adjusting the thickness of the film. FIG. 5shows schematically a portion of a high voltage transistor using aninduced channel 30 to control surface breakdown. The channel is N- andwas induced by the film of silicon dioxide 31 used to passivate thetransistor. The resistivity of this region and its thickness have beenadjusted by thinning the silicon dioxide 31 which is of a type havingpositive charge or its equivalent distributed through its volume. Athicker and stronger channel 32 exists beneath the heavier silicondioxide film 33. In some cases, any induced channel at the surface wouldbe of a nature as to raise the voltage at which surface avalanchebreakdown occurs and a thick oxide may be desirable, but where this isnot true, the surface resistivity and thus the surface breakdown voltagemay be increased by thinning the silicon dioxide adjacent the criticalchannel region. Obviously, for films having large surface chargedensities, the above considerations are subject to modification; forexample, a thin silicon dioxide film having on its surface a positivecharge or something similar, such as a film of a suitably oriented polarspecies of substance, would tend to form the stronger N type channelbeneath the thinner silicon dioxide film. The collector region 131 isformed on the substrate 132 in FIG. 5, and the reference characters 13%,133, and 134, identify, respectively, the base region, and two metalcontacts corresponding generally to those described for FIG. 4.

The two curves (FIG. 6) of electron concentration versus depth insilicon for thick and thin silicon dioxide films illustrate graphicallyhow the surface concentration of electrons is higher for some thicksilicon dioxide films. Also, the channel is thicker due to the mutualrepulsion of the electrons.

If the transistor of this invention is made to a specified BV a slightlylower bulk resistivity material in either or both the collector and basemay be used so that the series resistance of the transistor may be madelower than conventional transistors of an otherwise equivalent type.

Transistors having the base channel and the perimeter may be fabricatedin a number of ways so as to provide an improved high voltagetransistor. In the fabrication of the various device structuresdescribed herein, oxide films are present or are formed on the surfaceof the silicon during one or more high temperature operations. Underthese circumstances, as previously noted, redistribution of impurityused to dope the silicon occurs in accordance with its segregation anddiffusion coefficients with respect to the silicon and the oxide. Inorder that the channel of the finished transistor is characteristicallycorrect, the concentrations of dopants in the silicon adjacent theoxide-silicon interface are made initially either greater or less as arule than the desired final value in the channel. For example, if thechannel is to be high resistivity N type and the material used to dopethe silicon was phosphorus then a very high resistivity N region isrequired initially due to the snowplow effect; for a high resistivity Ptype channel where boron is the dopant, a lower resistivity P typestarting material is required.

In FIGS. 7 through 14 are illustrated the processing steps used inpreparing transistors in accordance with this invention. It should benoted that while in many cases the sequence of processing steps used inpreparing the structure of the active transistor elements is itself aprocessing requirement, occasionally it is not, so that it may bepossible in some cases to arrive at the same transistor structure usinga different sequence of steps. Also in FIGS. 7 through 14, thetransistors are treated for convenience in illustration and descriptionas if manufactured by performing operations on a single chip; however,in actual practice, a hundred or more active elements are usuallyfabricated at one time on a single wafer or substrate and are then cutapart into single active elements.

One method of preparing a transistor in accordance with this inventionis by the use of solid state diffusion and epitaxial procedures. This isillustrated in FIG. 7.

Selective diffusion (FIG. 7A) of N impurity through an opening 49 in afilm 41 of silicon dioxide is used to form the base region 42 (FIG. 7B)on the silicon 48. The glass film 43 was formed during the N diffusion.Openings 44 and 45 are (FIG. 7C) formed in the glass and silicon dioxidefilms which are then used to mask selectively for a P type diffusion inwhich the emitter 46 and perimeter 47 are formed. The silicon dioxideand glass films are then stripped off (FIG. 7D) and subsequently a layerof epitaxially formed silicon 50 (FIG. 7E) is grown at high temperaturesto form the channel. During the formation of the epitaxial region,impurity diffuses from the emitter 46, base 42, collector 48 andperimeter 47 so that all junctions extend to the surface. Part of theepitaxial material is then oxidized to form a layer 54 (FIG. 7F) ofsilicon dioxide which acts to protect and passivate the junctions of thetransistors. Openings 56 are made in the silicon dioxide layer (FIG. 7G)by appropriate techniques, and ohmic contacts 57, 58 and 59 (FIG. 7H) ofmetal are placed on the emitter, base and collector regions prior toassembly of the active element into a finished transistor device.

Another method is shown in FIG. 8. After the N type base region 61'(FIG. 8A) has been formed in the P type silicon 6%) by selectivediffusion, the silicon dioxide and glass (not shown) are stripped fromthe surface and a channel region 62 (FIG. 8B) of high resistivity N typesilicon is epitaxially grown on the surface of the wafer. This surfaceis then oxidized (FIG. 8C) to form a silicon dioxide film 63. Openings64 and 65 (FIG. 8D) are made in the silicon dioxide film 63 and theemitter 66 and the perimeter 67 are formed by selective diffusion (FIG.8E). The bulk of the oxide 68 formed during the emitter and perimeterdiffusion steps and the underlying silicon dioxide film 63 are left inplace on the active element for protective and passivation purposes butas in the device in FIG. 7, openings are made for the pur pose ofplacing metal contacts on the device. Subsequent processing is that ofany similar transistor.

In the following paragraphs relative to FIG. 9, the transister isdescribed both as a PNP, and an NPN device, and the conductivity tiypeshown in the drawing for illustrative purposes, is NPN.

Where it is not desirable to form the perimeter during the emitterdiffusion step and an epitaxial channel is required, the constructionshown in FIG. 9 can be used. The silicon 69 has a layer of silicondioxide 71 thereon, and selective perimeter diffusion through openings70 in silicon dioxide 71 may be accomplished first to deposit a thin Pregion 72 (FIG. 9A). During epitaxial formation of the N type channelmaterial 73 (FIG. 9B), the P impurity continues to diffuse and extendsto the surface through the epitaxial material to form the perimeter 74.The epitaxial surface layer 73 is oxidized to form an oxide film 77 andthen the base 75 and emitter 76 are formed by selective diffusion (or byother suitable techniques) as indicated in FIGS. 9C through 9E, and aswill be described.

In the preparation of NPN transistors requiring one or more thermaloxidation steps, the formation of an epitaxial P type channel has provedespecially useful in providing a superior way of avoiding the formationof the previously discussed N+ snowplow layer at the collector surfaceadjacent the base and the resulting reduction in the BV of thetransistor. An epitaxial film doped with a P type material grown acrossan N semiconductor die prior to oxidation and selective diffusion stepsprevents the formation of the N+ snowplow layer since the necessaryoxidation and formation of an oxidesilicon interface at the surface of Ntype silicon cannot occur simply because the N type material is maskedby the P type epitaxial film against the oxidizing atmosphere.

As an example of the manufacture of NPN high BV transistors, considerFIG. 9. The N type collector silicon 69 is first coated with a film ofsilicon dioxide 71 using a process which is operable at a temperaturesufficiently low that little oxidation of the silicon occurs. Byselective diffusion the perimeter 72 is formed; this is a very shortdiffusion and has little effect on the impurity distribution in thesilicon except in the region where the diffusion takes place. The oxide71 is then etched away in preparation for the deposition of theepitaxial film. The P type epitaxial film or channel 73 which typicallyis boron doped,.is formed and the perimeter is extended by diffusionthrough the film to form the thicker perimeter region 74. Selectivediffusion steps to form the P type base 75 and the N type emitter 76 aremade through the thermally grown oxide films 77 and 78. During thediffusion steps, oxide films 77, 78, and 178 will form as shown in thedrawings (FIGS. 9D and 9E). Since the channel 73 contains little, ifany, N type material such as phosphorus except in the region of theperimeter 74, r

the snowplow layer cannot occur.

In general, it is to be expected that uncompensated or properlycompensated P material covering N type material may be used to inhibitthe formation of N-lsnowplow layers. While P type epitaxial films workespecially well, the methods of forming the P type material for thispurpose is obviously not limited to epitaxial procedures. It may also benoted that it is not essential to diffuse the perimeter prior to growthof the P layer. If the P layer is first grown on the N substrate, theemitter, base and perimeter diffusions can then be performed in anydesired sequence except where the diffusion properties of the impuritymaterials or other process requirements dictate a sequence to befollowed.

The channel may be formed in a manner somewhat similar to that used informing the perimeter of FIG. 9. In FIG. a region 80 of N impurity hasbeen selectively diffused into the surface of P type silicon 88 (FIG.10A). A region 81 (FIG. 10B) of P type silicon is then grown epitaxiallyand the N region diffuses to the surface to form a channel 82 with theregion thereof nearer the surface being very lightly doped N material. Aregion 83 (FIG. 10C) of silicon dioxide is grown and a portion etchedaway and the N type base region 84 is formed by selective diffusion. Thesurface of the silicon is reoxidized to form a glass layer 85 during thediffusion operation and new openings 86 and 87 (FIG. 10D) are etched forthe selective diffusion operation in which the emitter 89 and perimeter90 are formed (FIG. 10E). Conventional processing methods are used tocomplete the device.

The channel may also be formed by diffusion, and the techniques formaking channels by diffusion in PNP transistors and NPN transistors aresignificantly different. The differences are primarily due to the natureof the channel forming impurities with respect to silicon and silicondioxide. This is illustrated in FIG. 11.

The diffused channel PNP transistor is prepared by first forming N typechannels 92 and 92' in the silicon 91 by diffusion (FIG. 11A). Theimpurity is arsenic due to the fact that it diffuses into silicon at avery slow rate. This diffusion is performed for just a short period oftime and then out-diffusion is begun to lower the surface concentrationof N impurity and thus raise the resistivity of the N type silicon atthe surface of the transistor to a high value. The channel 92 on thebottom of the silicon is etched or lapped away (FIG. 11B). Subsequently(FIGS. 11C through 11E), the silicon is reoxidized. Then the base 93,emitter 94 and perimeter 95 are formed by selective diffusion, andprocessing in the manner described previously is used to complete thedevice. During the diffusion steps, oxide layers 120 and 121 are formedas shown in the drawing.

An NPN transistor (FIG. 12) having a diffused channel may be prepared bydiffusing a channel using gallium as an impurity. The surface of thesilicon 106 has been selectively diffused to form the base 107 (FIG.12A) and the old silicon dioxide (not shown) etched away, then a newfilm of silicon dioxide 96 is grown. The emitter 97 (FIG. 12B) andperimeter 98 are formed by a selective diffusion of N impurity for ashort period of time. Subsequently, the device is exposed to gallium inanother diffusion step. The gallium diffuses through the silicon dioxidefilm 96 to form the channel region 99 (FIG. 12C). Sincethe galliumdiffusion step is of a short time, the emitter and perimeter are notseriously affected. The gallium diffused bottom surface (not shown) isthen etched or lapped completely away, and conventional pro cessing isused to complete the device.

Induced channels are readily formed and are very satisfactorily employedto increase the BV of a transistor. A simple PNP device structureutilizing the induced channel is shown in FIG. 13. Silicon dioxide 100is grown on high resistivity P type silicon 101 in such a manner as toinduce an N type channel 102 to form beneath the oxide (FIG. 13A). Bythermally growing the silicon dioxide in an atmosphere rich in Watervapor, a silicon dioxide film is formed which has a charge or chargedistribution such that it attracts electrons to the surface of thesilicon thus forming an N type channel 102. The base 103, emitter 104-and perimeter 105 are formed by selective diffusion (FIGS. 13B through13D) in the manner previously described.

Essentially the same transistor may be fabricated having a channel witha somewhat higher surface resistivity as illustrated in FIG. 14. Afterthe formation of the base region 109 by selective diffusion in thematerial 108, the channel 110 lying beneath the silicon dioxide 111 andglass 112 may be adjusted as to concentration and distribution ofelectrons so as to increase the resistivity at the surface of thesilicon by thinning the silicon dioxide and glass film. The oxide may beselectively etched away to the appropriate thickness by masking with aresist 113 and exposing the films 111 and 112 to hydrofluoric acid orsome equivalent such as hydrogen fluoride vapor for a period of time.Since it is only necessary that the breakdown voltage in the channel begreater than in the bulk material, the etching operation is not criticalsince the oxide need only be thinner than some given value. The channelmay also be adjusted by growing the oxide to the desired thickness. Theactive element is completed by selectively diifusing to form the emitter115 and the perimeter 116 and by putting on the metallic contacts (notshown).

Very clean surfaces of silicon and germanium tend to be P typeregardless of the conductivity type of the underlying bulk material, butin practice the conductivity type and resistivity of a surface aredependent on the processing history of the semiconductor material. Whena film of silicon dioxide is grown on a plane of monocrystallinesilicon, the conductivity type and strength of the underlying surfaceregion or channel is determined by the nature of the silicon dioxide.For example, steam grown silicon dioxide films tend to cause N typesilicon surfaces whereas pure oxygen grown films tend to cause P typesurfaces. At the present state-of-the-art, it would be somewhatdifficult to prepare a P or N type channel of a given surface carrierconcentration and distribution; however, since the transistors of thisinvention only require a surface resistivity above some minimum value,they are, in practice, easy to make.

In the manufacture of such PNP transistors, for example, processingmethods are selected to obtain a surface which is P type on the P regionwithin given limits of resistivity, and then a silicon dioxide film isstea-rn grown to the appropriate thickness so that by electronattraction the surface of the silicon is converted to N type with aresistivity at the surface above the minimum necessary to cause theavalanche breakdown to occur in the bulk.

In the case of an NPN device, the processing may be such as to form alow resistivity P type surface. Such surfaces will tend to be withingrossly specified resistivity limits. Then by forming over the surface asteam grown or electron attracting silicon dioxide film of anappropriate thickness, the P type material may be compensated by theelectrons induced to the surface by the silicon dioxide to a highresistivity P type channel.

If in either the PNP or NPN devices, the surface on which the channel isto be formed is initially N type, then, of course, oxygen grown, oralternatively an electron repelling silicon dioxide, is formed to theappropriate thickness either by growing or by etching so that theresistivity is above the critical value at the surface in the case ofthe PNP transistor, and for conversion of the surface to highresistivity P type in the case of the NPN transistor.

Transistors fabricated according to the preceding description constitutean improvement over conventional transistors since their design permitsoperation at higher voltages than conventionl transistors of anotherwise equivalent type. Such transistors having a specified BV ofthat of conventional transistors also constitutes an improvement sincethey may be manufactured wit-h a lower series resistance than theconventional devices.

Another important improvement of these devices is that theirconstruction is such that exposure to environments which tend to inducechannel formation generally has only a slight effect on these devicessince the perimeter interrupts the condition path of such channels.

I claim:

1. In the method of fabricating a semiconductor device which has desiredreverse current and breakdown voltage characteristics,

(a) providing a silicon semiconductor element having a first regioncontaining a first impurity which imparts a predetermined resistivityand a predetermined conductivity type to said region,

(b) forming a channel region at the top surface of said first regionwith one face of said channel region contiguous with said first region,such channel region having a second impurity therein which imparts aconductivity type opposite to that of said first region and aresistivity higher than that of said first region, and which has asegregation coefiicient such that said second impurity segregates to atleast as high a concentration in a silicon dioxide insulating coatingthat is grown over the entire top surface of said element as in thesilicon of said channel region, with said channel region preventingoxidation of the portion of the first region contiguous with saidchannel region during the growth of an insulating oxide coating on saidtop surface to maintain the original resistivity of said first region,

(c) growing an insulating coating of silicon dioxide over the entire topsurface of said semiconductor element immediately above said channelregion,

((1) forming an opening in said coating down to the semiconductorelement,

(e) diffusing through said opening and said channel region into saidfirst region a second region contain ing a third impurity and extendingupwardly to the insulating coating and being of opposite conductivitytype to that of said first region, with a junction being formed at theinterface of said first and second regions,

(f) growing an insulating coating of silicon dioxide over the entire topsurface of said semiconductor element,

(g) forming an opening in said latter insulating coating down to thesemiconductor element, and

(h) forming a channel-interrupting region through said latter mentionedopening which extends downwardly from said top surface through saidchannel region into said first region to structurally block andinterrupt said channel region over the entire depth thereof from saidtop surface, with said channel-interrupting region spaced laterally awayand separated from said second region and completely surrounding saidsecond region, and being of the same conductivity type as the firstregion and of lower resistivity than the same.

2. In the method of claim 1, wherein two openings are formed in theinsulating coating of paragraph (g), and forming a third region whollywithin the second region through one of said two openings at the sametime as said channel-interrupting region is formed through the other ofsaid two openings and of the same conductivity type as that of saidchannel-interrupting region.

3. In the method of claim 2 wherein said first, said third, and saidchannel-interrupting regions are each of N conductivity type, and saidsecond region and said channel region are of P conductivity type.

4. In the method of claim 2 wherein said first, said third, and saidchannel-interrupting regions are each of P conductivity type, and saidsecond region and said channel region are of N conductivity type.

5. In the method of fabricating a semiconductor device Which has desiredreverse current and breakdown voltage characteristics,

(a) providing a silicon semiconductor element having a first regioncontaining a first impurity which imparts a predetermined resistivityand a predetermined conductivity type to said region,

(b) growing an insulating coating on the entire top surface of saidfirst region in a manner such that little oxidation occurs,

(c) forming an opening in said insulating coating of little oxidation,

(d) forming a channel-interrupting region through said opening, saidchannel-interrupting region having a conductivity type the same as thatof said first region and a resistivity lower than that of said firstregion,

(e) forming a channel region on the top surface of said first region ofan opposite conductivity type to that of said first region, with saidchannel-interrupting region diffusing upwardly through said channelregion to the top surface of said semiconductor element during theforming of said channel region.

(f) forming an insulating coating over the entire top surface of saidsemiconductor element,

(g) forming an opening in said latter insulating coating,

and

(h) diltusing through said latter opening a second region of the sameconductivity type as said channel region with said channel regionextending outwardly therefrom underneath the insulating coating andterminating at said channel-interrupting region.

6. In the method of claim 5, wherein another insulating coating isformed over the entire top surface of the semi conductor elements,forming an opening in said another coating over said second region, anddiffusing through said last mentioned opening a third region whollywithin the second region and of the same conductivity type as that ofsaid channel-interrupting region.

7. In the method of claim 6 wherein said first, said third, and saidchannel-interrupting regions are of N conductivity type, and said secondregion is of P conductivity type.

8. In the method of claim 6 wherein said first, said third, and saidchannel-interrupting regions are of P conductivity type, and said secondregion is N conductivity type.

9. In the method of fabricating a semiconductor device which has desiredreverse current and breakdown voltage characteristics,

(a) providing a silicon semiconductor element having a first regioncontaining a first impurity which imparts a predetermined resistivityand an N conductivity type to said region,

(b) growing an insulating coating on the entire top surface of saidfirst region,

(c) forming an opening in said insulating coating,

(d) diffusing through said opening into said first region,

a second region containing a second impurity and being of P conductivitytype and forming a junction with said first region,

(e) growing an insulating coating of silicon dioxide over the entire topsurface of said semiconductor element,

(f) forming an opening in said latter insulating coating down to thesemiconductor element, with said opening being over said first regionand spaced away from said junction and completely surrounding the same,

(g) diffusing through said latter opening into said first region, athird region of N conductivity type extending from said top surface ofsaid element downwardly and forming a channel-interrupting region of adepth which structurally blocks and interrupts any channel region formedin said element.

(h) growing an insulating coating of silicon dioxide over the entire topsurface of said semiconductor element, and

(i) diffusing a channel region through said last men tioned coatingusing gallium impurity therein which imparts a P conductivity type tosaid channel region and a resistivity higher than that of said firstregion, said channel region forming a junction with said first regionand said channel-interrupting region, and being diffused to a depth lessthan that of said channel-interrupting region.

10. In the method of claim 9, wherein two openings are formed in theinsulating coating of paragraph (f) with the second of said openingsbeing over said second region, and forming a fourth region of Nconductivity type through said second opening wholly within said secondregion and at the same time that said third region is formed by thediffusion of paragraph (g).

References Cited by the Examiner UNITED STATES PATENTS 2,462,218 2/1949Olsen l48l91 3,085,033 4/1963 Handelman 148l9l 3,165,811 1/1965 Kleimack148-188 3,183,128 5/1965 Leistiko 148l87 3,183,129 5/1965 Tripp 148-187HYLAND BIZOT, Primary Examiner.

1. IN THE METHOD OF FABRICATING A SEMICONDUCTOR DEVICE WHICH HAS DESIREDREVERSE CURRENT AND BREAKDOWN VOLTAGE CHARACTERISTICS, (A) PROVIDING ASILICON SEMICONDUCTOR ELEMENT HAVING A FIRST REGION CONTAINING A FIRSTIMPUIRTY WHICH IMPARTS A PREDETERMINED RESISTIVITY AND A PREDETERMINEDCONDUCTIVITY TYPE TO SAID REGION, (B) FORMING A CHANNEL REGION AT THETOP SURFACE OF SAID FIRST REGION WITH ONE FACE OF SAID CHANNEL REGIONCONTIGUOUS WITH SAID FIRST REGION, SUCH CHANNEL REGION HAVING A SECONDIMPURITY THEREIN WHICH IMPARTS A CONDUCTIVITY TYPE OPPOSITE TO THAT OFSAID FIRST REGION AND A RESISTIVITY HIGHER THAN THAT OF SAID FIRSTREGION, AND WHICH HAS A SEGREGATION COEFFICIENT SUCH THAT SAID SECONDIMPURITY SEGREGATES TO AT LEAST AS HIGH A CONCENTRATION IN A SILICONDIOXIDE INSULATING COATING THAT IS GROWN OVER THE ENTIRE TOP SURFACE OFSAID ELEMENT AS IN THE SILICON OF SAID CHANNEL REGION, WITH SAID CHANNELREGION PREVENTING OXIDATION OF THE PORTION OF THE FIRST REGIONCONTIGUOUS WITH SAID CHANNEL REGION DURING THE GROWTH OF AN INSULATINGOXIDE COATING ON SAID TOP SURFACE TO MAINTAIN THE ORIGINAL RESISTIVITYOF SAID FIRST REGION, (C) GROWING AN INSULATING COATING OF SILICONDIOXIDE OVER THE ENTIRE TOP SURFACE OF SAID SEMICONDUCTOR ELEMENTIMMEDIATELY ABOVE SAID CHANNEL REGION, (D) FORMING AN OPENING IN SAIDCOATING DOWN TO THE SEMICONDUCTOR ELEMENT, (E) DIFFUSING THROUGH SAIDOPENING AND SAID CHANNEL REGION INTO SAID FIRST REGION A SECOND REGIONCONTAINING A THIRD IMPURITY AND EXTENDING UPWARDLY TO THE INSULATINGCOATING AND BEING OF OPPOSITE CONDUCTIVITY TYPE TO THAT OF SAID FIRSTREGION, WITH A JUNCTION BEING FORMED AT THE INTERFACE OF SAID FIRST ANDSECOND REGIONS, (F) GROWING AN INSULATING COATING OF SILICON DIOXIDEOVER THE ENTIRE TOP SURFACE OF SAID SEMICONDUCTOR ELEMENT, (G) FORMINGAN OPENING IN SAID LATTER INSULATING COATING DOWN TO THE SEMICONCUDTORELEMENT, AND (H) FORMING A CHANNEL-INTERRUPTING REGION THROUGH SAIDLATTER MEMTIONED OPEING WHICH EXTENDS DOWNWARDLY FROM SAID TOP SURFACETHROUGH SAID CHANNEL REGION INTO SAID FIRST REGION TO STRUCTURALLY BLOCKAND INTERRUPT SAID CHANNEL REGION OVER THE ENTIRE DEPTH THEREOF FROMSAID TOP SURFACE, WITH SAID CHANNEL-INTERRUPTING REGION SPACED LATERALLYAWAY AND SEPARATED FROM SAID SECOND REGION AND COMPLETELY SURROUNDINGSAID SECOND REGION, AND BEING OF THE SAME CONDUCTIVITY TYPE AS THE FIRSTREGION AND OF LOWER RESISTIVITY THAN THE SAME.